The use of a binary weighted capacitor array to perform analog to digital (A/D) and digital to analog (D/A) conversions is known in the field of integrated circuits. Prior conventional techniques for such conversions required both high performance analog and digital circuitry which cannot be economically accommodated on a single integrated circuit. The capacitor array conversion circuit is discussed in detail in "All-MOS Charge Redistribution Analog-to-Digital Conversion Techniques - Part I" published in the IEEE Journal of Solid-State Circuits, Vol. SC-10, No. 6, December 1975, and authored by J. L. McCreary and P. R. Gray. This article is incorporated herein by reference.
Thereafter, a new conversion structure evolved consisting of a two-stage weighted capacitor network 10, shown in FIG. 1. Two-stage network 10 includes a most significant bits (MSB) stage 12 and a least significant bits (LSB) stage 13. Each stage 12 and 13 includes a predetermined number of capacitors 14-18 and 20-25, respectively. Capacitors 14-18 and 20-25 are binary weighted, i.e. if the capacitances of capacitors 20, 21 and 14 are C, then the capacitances of capacitors 22 and 15 are 2C (or 2.sup.1 * C), the capacitances of capacitors 23 and 16 are 4C (or 2.sup.2 * C), the capacitances of capacitors 24 and 17 are 8C (or 2.sup.3 * C), and the capacitances of capacitors 25 and 18 are 16C (or 2.sup.4 * C). The two stages 12 and 13 are connected by a coupling capacitor 27, the value of which is equal to ##EQU1## A comparator 28 is connected in its inverting configuration to MSB network 12. A switching matrix 29, generally consisting of switches, alternatively couples capacitors 14-18 and 20-25 to an input voltage V.sub.IN and reference voltages V.sub.REF+ and V.sub.REF-. The output 32 of comparator 28 provides the converted signal. The two-stage capacitor network is discussed in detail in "A Two-Stage Weighted Capacitor Network for D/A - A/D Conversion" published in IEEE Journal of Solid-State Circuits, Vol. SC-14, No. 4, August 1979, and authored by Y. S. Yee, L. M. Terman, and L. G. Heller, incorporated herein by reference.
The two-stage capacitor network 10 is a more desirable implementation because it requires a smaller range of capacitor values than the single array configuration and therefore requires less die area. However, the two-stage A/D converter is still plagued by a well known phenomenon, the fringing effect, which causes substantial inaccuracy in A/D converters. The fringing effect is caused by the electric field of the top plate of a capacitor in the array 14-18 and 20-25 coupling with the bottom plate of other capacitors in addition to its own bottom plate. Fringing effect may also be caused by coupling of the top plate to some other potential in the network structure. Additional contribution to the fringing effect comes from the coupling of potentials in the coupling capacitor to other potentials in the network. The end result of the fringing effect is mismatch of capacitances of the capacitors 14-18 and 20-25 and coupling capacitor 27 in the network which upsets the binary weighting requirement of the converter 10.
Known solutions to the inaccuracy induced by the fringing effect include using either a sandwich capacitor structure or adding a conductive shield. In the former method, each capacitor 14-18, 20-25 and including the coupling capacitor 27 are implemented as sandwich capacitors. Although the fringing effect is reduced significantly, additional mismatch among the capacitors is introduced by the sandwich structure. The additional mismatch is caused by the non-uniformity of the oxide layer between the metal sandwiching layer and the top plate of each capacitor. Non-uniformity of the oxide layer is common as its formation is not closely monitored.
Another possible solution to the problem is to add a conductive shield over the entire capacitor array and tie the shield to a fixed potential, such as ground. This solution overcomes the oxide non-uniformity problem associated with the sandwich capacitor solution described above, yet it introduces other factors which contribute to the inaccuracy of the converter 10. For example, parasitic capacitance is introduced between the shielding layer and the top plates of the capacitors. Therefore, the capacitance value of the coupling capacitor 27 must account for the parasitic capacitance. Computations have shown that the coupling capacitor capacitance should be equal to 32(C+C.sub.p)/31 for the capacitor network shown in FIG. 1, where C.sub.p is the parasitic capacitance associated with each unit capacitance C. However, because the oxide thickness between the conductive shield layer and top plates (which contributes to C.sub.p) does not track the oxide thickness between the top plate and bottom plate (which contributes to C), the problem of mismatch and inaccuracy results. For additional discussions of problems associated with the capacitor network implementation, please refer to "Fully Differential ADC with Rail-to-Rail Common-Mode Range and Nonlinear Capacitor Compensation" published in IEEE Journal of Solid-State Circuits, Vol. 25, No. 1, February 1990, and authored by R. K. Hester, K. S. Tan, M. de Wit, J. W. Fattaruso, S. Kiriaki, and J. R. Hellums. This article is hereby incorporated by reference.
Therefore, a need has arisen for a solution to the fringing effect and mismatching problem in the weighted capacitor array A/D or D/A converter. The present invention provides a technique for enhancing capacitance matching among the capacitors in the array and thereby contributing to more accuracy and resolution in the A/D or D/A conversion process.